View TDA9177_1067520.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

product speci?cation supersedes data of 1996 jun 28 file under integrated circuits, ic02 1997 dec 01 integrated circuits TDA9177 yuv transient improvement processor d a t a sh eet
1997 dec 01 2 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 features can be used in 1f h and 2f h applications luminance step improvement line width control smart peaking for detail enhancement embedded feature reduction facility for smart noise control compensating chrominance delay yuv interface two additional pins for access to 6-bit adc and i 2 c-bus versatile i 2 c-bus and pin control for user adjustments. general description the TDA9177 is an i 2 c-bus controlled sharpness improvement ic with additional inputs for 6-bit analog-to-digital conversion to facilitate additional parameter measurement (e.g. ambient light control). it should preferably be used in front of an rgb video signal processor with yuv interface. in combination with the tda9170, it builds a high performance and intelligent picture improvement solution. the sharpness processor provides 1d luminance step improvement and detail enhancement by smart peaking, suitable for both 1f h and 2f h applications. the TDA9177 can be used as a cost effective alternative to (but also in combination with) scan velocity modulation (svm). an on-board 6-bit analog-to-digital converter (adc) can be used for interfacing two analog, low frequency voltage signals to the i 2 c-bus. the supply voltage is 8 v. the TDA9177 is mounted in a 24-pin sdip envelope. quick reference data ordering information symbol parameter conditions min. typ. max. unit v cc supply voltage 7.2 8.0 8.8 v v i(y) luminance input voltage ams = low - 0.315 0.42 v ams = high - 1.0 1.33 v v i(uv) uv input voltage -- 1.9 v v fs(adc) full scale adc input voltage - 0.5v ref - v v ref reference voltage 3.90 4.05 4.20 v type number package name description version TDA9177 sdip24 plastic shrink dual in-line package; 24 leads (400 mil) sot234-1
1997 dec 01 3 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 block diagram fig.1 block diagram. handbook, full pagewidth mbh229 step improvement processor smart sharpness controller contour processor clamps delay delay delay iptat bandgap black insertion clamp amplitude selection uin yin sandcastle input uout vin vout r ext v cc gnd sandcastle detector i 2 c-bus controller ams cfs fhs pin-to-i 2 c-bus interface 6-bit adc contour filter selection line frequency selection line width steepness coring peaking 24 9 18 16 7 5 1 peak 11 lwc steep 4 22 14 8 17 sda 13 adr 6 scl 12 adext2 TDA9177 10 adext1 3 cor 2 21 19 v ref snc yout 23 15 20
1997 dec 01 4 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 pinning symbol pin description sandcastle 1 sandcastle input cor 2 coring level input adext1 3 adc input 1 lwc 4 line width control input yin 5 luminance input adr 6 i 2 c-bus address input uin 7 colour u input cfs 8 contour ?lter select input vin 9 colour v input adext2 10 adc input 2 peak 11 peaking amplitude input scl 12 serial clock input (i 2 c-bus) sda 13 serial data input/output (i 2 c-bus) ams 14 amplitude select input snc 15 smart noise control input vout 16 colour v output fhs 17 line frequency select input uout 18 colour u output gnd 19 system ground yout 20 luminance output v cc 21 supply voltage steep 22 steepness control input v ref 23 reference voltage output r ext 24 resistor reference fig.2 pin configuration. handbook, halfpage TDA9177 mbh228 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 sandcastle cor adext1 adext2 peak scl fhs sda ams snc lwc yin adr uin cfs vin r ext v ref v cc vout uout gnd yout steep
1997 dec 01 5 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 functional description y-input selection and ampli?cation the dynamic range of the luminance input amplifier and output amplifier can be switched between 0.315 v and 1.0 v typically (excluding sync), either externally (pin ams) or by i 2 c-bus (bit ams of the control register). amplitudes outside the corresponding maximum specified range will be clipped smoothly. the sync part is processed transparently to the output, independently of the feature settings. the input is clamped during the high period of the clp, defined by the sandcastle reference, and should be dc-decoupled with an external capacitor. during the clamp pulse, an artificial black level is inserted in the input signal to correctly preset the internal circuitry. the input amplifier drives a delay line of four delay sections, which form the core of the sharpness improvement processor. sharpness improvement processor the sharpness improvement processor increases the slope of large luminance transients of vertical objects and enhances transients of details in natural scenes by contour correction. it comprises three main processing units, these being the step improvement processor, the contour processor and the smart sharpness controller. s tep improvement processor the step improvement processor (see fig.9) comprises two main functions: 1. the minmax generator 2. the minmax fader. the minmax generator utilizes 5 taps of an embedded luminance delay line to calculate the minimum and maximum envelope of all signals momentarily stored in the delay line. the minmax fader chooses between the minimum and maximum envelopes, depending on the polarity of a decision signal derived from the contour processor. figures 4, 5 and 6 show some waveforms of the step improvement processor and illustrate that fast transients result with this algorithm. the minmax generator also outputs a signal that represents the momentary envelope of the luminance input signal. this envelope information is used by the smart sharpness controller. limited line width control (also called aperture control) can be performed externally (pin 4, lwc) or by i 2 c-bus (lw-dac). line width control can be used to compensate for horizontal geometry because of the gamma or blooming of the spot of the crt. t he contour processor the contour processor comprises two contour generators with different frequency characteristics. the contour generator generates a second-order derivative of the incoming luminance signal and is used both as a decision signal for the step improvement processor and as a luminance correction signal for the smart sharpness controller. in the smart sharpness controller, this correction signal is added to the proper delayed original luminance input signal, making up the peaking signal for detail enhancement. the peaking path is allowed to select either the narrow- or wide-peaked contour generators either externally (pin 8, cfs) or by i 2 c-bus (bit cfs in the control register). the step improvement circuitry always selects the wide-peaked contour filter. the contour generators utilize 3 taps (narrow band) or 5 taps (broad band) of the embedded luminance delay lines. figures 11 and 12 illustrate the normalized frequency transfer of both the narrow and wide contour filters. s mart sharpness controller the smart sharpness controller (see fig.10) is a fader circuit that fades between peaked luminance and step-improved luminance, defined by the output of a step discriminating device known as the step detector. it also contains a variable coring level stage. the step detector behaves like a band-pass filter, so both amplitude of the step and its slope add to the detection criterion. the smart sharpness controller has four user controls: 1. steepness control 2. peaking control 3. coring level control 4. smart noise control. control settings can be performed either by the i 2 c-bus or externally by pin, depending on the status of the i 2 c-bus bit stb. the steepness setting controls the amount of steepness in the edge-correction processing path. the peaking setting controls the amount of contour correction for proper detail enhancement.
1997 dec 01 6 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 the envelope signal generated by the step improvement processor modulates the peaking setting in order to reduce the amount of peaking for large sine excursions see figs 7 and 8. the coring setting controls the coring level in the peaking path for rejection of high-frequency noise. all three settings facilitate reduction of the impact of the sharpness features, e.g. for noisy luminance signals. an external noise detector and a user-preferred noise algorithm are needed to make a fully automatic i 2 c-bus controlled smart sharpness control. an on-board, hard-wired smart sharpness algorithm can be executed by driving pin snc with the output of an external noise detector. this pin, however, is active both in i 2 c-bus and pin mode. figures 13 and 14 illustrate the impact of the noise control voltage at pin snc on the user settings. figure 15 shows the relationship between the feature settings steep, cor, peak, lwc and their corresponding pin voltages. chrominance compensation the chrominance delay lines compensate for the delay of the luminance signal in the step improvement processor, to ensure a correct colour fit. no delay compensation will be performed in the chrominance path for line-width corrections in the luminance path. successive approximation adc pins adext1 and adext2 are connected to a 6-bit successive approximation adc, via a multiplexer. the multiplexer toggles between the inputs with each field. for each field flyback, a conversion is started for either of the two inputs and the result is stored in the corresponding bus register, adext1 or adext2. in this way, any analog, slowly varying signal can be given access to the i 2 c-bus. if a register access conflict occurs, the data of that register is made invalid by setting the flag bit dv (data valid) to zero. i 2 c-bus at power up, the bit stb (standby) in the control register is reset, to leave control to the pins. however, the i 2 c-bus is at standby and responds if properly addressed. by setting stb to logic 1, the control of all features is instead left to the i 2 c-bus registers. the pdd bit (power down detected) in the status register is set each time an interruption of the supply power occurs and is reset only by reading the status register. a 3-bit identification code can also be read from the status register, which can be used to automatically configure the application by software. the input control registers can be written sequentially by the i 2 c-bus by the embedded automatic subaddress increment feature or by addressing it directly. the output control functions cannot be addressed separately. reading out the output control functions always starts at subaddress 00 and all subsequent words are read out by the automatic subaddress increment procedure. the i 2 c address is 40h if pin 6 (adr) is connected to ground and e0h if pin 6 (adr) is connected to pin 23 (v ref ). i 2 c-bus speci?cation slave address auto-increment mode available for subaddresses. a6 a5 a4 a3 a2 a1 a0 r/w adr 1 adr 0 0 0 0 x
1997 dec 01 7 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 control functions functions type subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 inputs control reg 00 x x x x cfs fhs ams stb peaking dac 01 x x pk5 pk4 pk3 pk2 pk1 pk0 steepness dac 02 x x sp5 sp4 sp3 sp2 sp1 sp0 coring dac 03 x x cr5 cr4 cr3 cr2 cr1 cr0 line width dac 04 x x lw5 lw4 lw3 lw2 lw1 lw0 outputs status reg 00 0 0 0 0 id2 id1 id0 pdd adext1 (output) reg 01 0 dv ad5 ad4 ad3 ad2 ad1 ad0 adext2 (output) reg 02 0 dv ad5 ad4 ad3 ad2 ad1 ad0 i nput signals table 1 address selection table 2 standby table 3 amplitude selection table 4 line frequency selection table 5 contour ?lter selection adr function 0i 2 c address is 40h 1i 2 c address is e0h stb function 0 pin mode 1i 2 c-bus mode ams function 0 0.315 v luminance 1 1.0 v luminance fhs function 01f h 12f h cfs function 0 narrow contour ?lter 1 wide contour ?lter table 6 peaking amplitude table 7 steepness correction table 8 coring level table 9 line width correction pk5 to pk0 function 000000 0% 111111 100% sp5 to sp0 function 000000 0% 111111 100% cr5 to cr0 function 000000 0% 111111 100% lw5 to lw0 function 000000 0% 111111 100%
1997 dec 01 8 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 o utput signals table 10 power down detection (pdd) table 11 identi?cation (version number or derivative type) pdd function 0 no power down detected since last read action 1 power down detected id2 to id0 function 000 TDA9177/n1 table 12 data valid of adc registers table 13 bits ad5 to ad0 dv function 0 data not valid because of possible register access collision 1 data valid ad5 to ad0 function 000000b 0 v 111111b 0.5v ref limiting values in accordance with the absolute maximum rating system (iec 134). quality specification quality level in accordance with snw-fq-611 part e . all pins are protected against esd by means of internal clamping diodes. the protection circuit meets the specification: human body model (100 pf, 1500 w ): all pins >3000 v. machine model (200 pf, 0 w ): all pins >300 v. latch-up: at an ambient temperature of 70 c, all pins meet the specification: i trigger > 100 ma or v pin > 1.5v cc(max) i trigger < - 100 ma or v pin < - 0.5v cc(max) thermal characteristics symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +8.8 v v i input voltage on any input - 0.5 v cc + 0.5 v v o output voltage of any output - 0.5 v cc + 0.5 v t stg storage temperature - 55 +150 c t amb operating ambient temperature - 10 +70 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air <59 k/w
1997 dec 01 9 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 characteristics v cc =8v; r ref =10k w 2%; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies m ain supply v cc ( pin 21) v cc supply voltage 7.2 8.0 8.8 v i cc supply current 1f h mode - 40 - ma 2f h mode - 45 - ma r eference supply v ref ( pin 23) v ref reference supply voltage 3.90 4.05 4.20 v i l(max) maximum load current 1.0 -- ma r esistor reference r ext ( pin 24) v rref resistor supply voltage - 2 - v r ref resistor value - 10 - k w luminance input/output selection l uminance input yin ( pin 5) v i(y) luminance input voltage ams = low - 0.315 0.42 v ams = high - 1.0 1.33 v v i(yclamp) luminance input voltage level during clamping - 4.0 - v i ib(y) luminance input bias current no clamp -- 0.1 m a l uminance input voltage range selection ams ( pin 14); note 1 v amsl input voltage for low luminance range -- 0.5 v v amsh input voltage for high luminance range 3.5 - 5.5 v
1997 dec 01 10 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 l uminance output yout ( pin 20) v o(y) (p-p) luminance output voltage, peak-to-peak ams = low - 0.315 - v ams = high - 1.0 - v v o(yclamp) luminance output voltage during clamping ams = low - 2.35 - v ams = high - 2 - v s/n(y) luminance output signal-to-noise ratio 52 -- db b y luminance bandwidth 1f h mode ( - 1 db); transparent; note 2 5 -- mhz 2f h mode ( - 1 db); transparent; note 2 10 -- mhz e bl black level error transparent; note 3 - 0 1.0 % e g(n) nominal gain error transparent - 05% r out output resistance -- 150 w i ob output bias current 1.3 -- ma step improvement g eneral t r(min) minimum rise time 10% to 90% 1f h mode; note 4 - 20 - ns 2f h mode; note 4 - 20 - ns l ine width control d (min) minimum duty factor 2 mhz - 33 - % d (max) maximum duty factor 2 mhz - 67 - % t sd(max) maximum step displacement 1f h mode - 140 - ns 2f h mode - 70 - ns l ine - width control lwc ( pin 4); note 1 v i(min) input voltage for minimum line width -- 37.5 %v ref v i(max) input voltage for maximum line width 87.5 - 137.5 %v ref i bias input bias current - 0.5 -m a contour processing c ontour filter narrow - peaked f pc peaking centre frequency 1f h - 3.57 - mhz 2f h - 7.14 - mhz c ontour filter wide - peaked f pc1 peaking centre frequency 1f h - 4.14 - mhz 2f h - 8.28 - mhz q max maximum contour amplitude at centre frequency note 5 - 12 - db symbol parameter conditions min. typ. max. unit
1997 dec 01 11 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 c ontour filter selection cfs ( pin 8); note 1 v i(ncf) input voltage for narrow contour ?lter -- 0.5 v v i(wcf) input voltage for wide contour ?lter 3.5 - 5.5 v smart sharpness controller s tep detector f dc detection centre frequency 1f h - 2.13 - mhz 2f h - 4.26 - mhz c oring q smcl minimum coring level note 6 - 0 - % q smch maximum coring level note 6 - 22 - % c oring level control cor ( pin 2); note 1 v i(min) input voltage for minimum coring -- 37.5 %v ref v i(max) input voltage for maximum coring 87.5 - 137.5 %v ref i bias input bias current -- 0.5 m a p eaking level control peak ( pin 11); note 1 v i(min) input voltage for minimum peaking -- 37.5 %v ref v i(max) input voltage for maximum peaking 87.5 - 137.5 %v ref i bias input bias current -- 0.5 m a s teepness level control steep ( pin 22); note 1 v i(min) input voltage for minimum steepness -- 37.5 %v ref v i(max) input voltage for maximum steepness 87.5 - 137.5 %v ref i bias input bias current -- 0.5 m a s mart noise control snc ( pin 15) v nfr level for no feature reduction - 0.0 - v v cfr level for complete feature reduction - v ref - v i bias input bias current -- 1.0 m a overall group delay performance for luminance t d delay time from input to output 1f h mode - 175 - ns 2f h mode - 108 - ns t de delay error contour correction 1f h mode; note 7 - 010ns 2f h mode; note 7 - 05ns t de1 delay error step correction 1f h mode; note 7 - 010ns t de2 delay error step correction 2f h mode - 05ns symbol parameter conditions min. typ. max. unit
1997 dec 01 12 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 d elay time selection fhs ( pin 17); note 1 v i1fh input voltage for 1f h -- 0.5 v v i2fh input voltage for 2f h 3.5 - 5.5 v colour difference processing c olour difference inputs uin and vin ( pins 7 and 9) v iuin(p-p) input voltage range uin, peak-to-peak 1.9 -- v v ivin(p-p) input voltage range vin, peak-to-peak 1.9 -- v i bias input bias current uin, vin no clamp -- 0.1 m a v cl voltage level during clamping - 4.0 - v c olour difference outputs uout and , vout ( pins 18 and 16) v o(cl) output voltage level during clamping - 3.2 - v g gain - 1.0 - e off offset error transparent - 01% e g gain error transparent - 05% e g(uv) uv gain tracking error transparent - 01% b bandwidth 1f h 7 -- mhz 2f h 7 -- mhz t d delay time 1f h - 175 - ns 2f h - 108 - ns r out output resistance -- 150 w i ob output bias current 0.5 -- ma successive approximation adc adext1 and adext2 ( pins 3 and 10) v fs full scale input voltage range with respect to gnd - 2.0 - v i ib input bias current -- 1 m a data path - 6 - bit dle differential linearity error -- 1 lsb ile integral linearity error -- 1 lsb f con conversion frequency each channel - 0.5f v - hz q adt conversion time (video lines) each channel - 8 - lines symbol parameter conditions min. typ. max. unit
1997 dec 01 13 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 notes 1. this selection is only valid when the standby bit stb is not set. 2. in transparent mode i.e. no step improvement and no peaking, the bandwidth of the luminance path for which the group delay is constant is 7 mhz in 1f h mode and 14 mhz in 2f h mode. however, as the circuit uses all-pass filters, ringing on the output signal may occur if the bandwidth of the input signal is larger than 7 mhz in 1f h mode or 14 mhz in 2f h mode. as the step improvement circuit adds harmonics to the luminance signal, the bandwidth of the output signal is much larger than 14 mhz. 3. the black level error that may occur will mainly be caused by inaccuracies in the internal clamping circuit. this internal clamping circuit is activated during 70% of the duration of the burst key pulse on the sandcastle signal. integration of the ramp shaped black level error during the full duration of the burst key pulse will reduce the black level error to less than 1%. 4. peaking set to minimum. input signal is a sine wave with the nominal peak-to-peak amplitude corresponding to the selected input range. 5. the contour signal cannot be measured separately from the luminance input signal. the contour signal is also processed by the smart noise controller. the frequency transfer in the peaking mode of the luminance signal can be derived from the frequency transfer of the selected contour signal, taking into account the summation of the contour signal and the luminance input signal. the frequency transfer is most easily measured by sine excitation with a relatively small signal amplitude of 10% of the selected dynamic range of the luminance input, to avoid interaction with the step detector. 6. the coring level refers to the internally selected contour signal. it is dependent on the contour filter selected and is specified for the corresponding peaking centre frequency. the coring level can not be measured explicitly at the luminance output from a big step or sine excitation, because of its interaction with the step detector. 7. contour correction and step improvement delays are internal delays and cannot be measured in a straightforward way. contour correction delay mismatch results in asymmetrical ears with respect to the centre of the transient. step improvement correction delay mismatch affects the symmetry of the line width control. timing s andcastle input sandcastle ( pin 1) v scbn detection level for blank no clamping 1.25 1.5 1.75 v v scbc detection level for blank with clamping and w.r.t. top level sandcastle pulse -- 0.6 - v t scnv input blanking width for no v-sync -- 15 m s t scv input blanking width for v-sync 35 --m s v bkvar ripple on sandcastle burst key level -- 0.4 v overall output group delay performance t dm(yuv) delay of matching yuv 1f h - 010ns 2f h - 05ns symbol parameter conditions min. typ. max. unit
1997 dec 01 14 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 figures 3 to 8 show the excitation and response of the TDA9177 sharpness improvement processor. the excitation shown in fig.3 is a 2t-pulse, followed by a step function. because the TDA9177 can handle both 1f h and 2f h signals, figures illustrating both situations could have been provided. however, as the difference between these two modes (with respect to the TDA9177) is that the time scale of a 2f h response diagram is half that of a 1f h response diagram under equal conditions, only the 1f h figures are shown. figure 4 shows that the step improvement processor does not affect small amplitudes. large transients, however, acquire steeper edges. figures 5 and 6 show that the width of the signal processed by the step improvement processor can be modified by the line width control pin lwc (or daclw). figure 7 shows that the contour processor does not affect large transients, but works exclusively on small signals, e.g. details in a video signal. figure 8 shows the combination of smart peaking and the step improvement processor; small signals will be affected by the contour processor, while large transients will be modified by the step improvement processor.
1997 dec 01 15 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 fig.3 excitation signals: 90% and 30% of nominal amplitude 2t-pulse and step function. (1) 90% of nominal amplitude. (2) 30% of nominal amplitude. handbook, halfpage 0 0.5 1000 800 200 0 400 600 mbh230 1.0 (1) (2) 1.5 2.0 t ( m s) input signal (mv) fig.4 response signals for maximum step improvement, no peaking and nominal line width. handbook, halfpage 0 0.5 1000 800 200 0 400 600 mbh231 1.0 1.5 2.0 t ( m s) (1) (2) v o (mv) (1) 90% of nominal amplitude. (2) 30% of nominal amplitude. fig.5 response signals for maximum step improvement, no peaking and minimum line width. handbook, halfpage 0 0.5 1000 800 200 0 400 600 1.0 1.5 2.0 t ( m s) v o (mv) (1) (2) mbh232 (1) 90% of nominal amplitude. (2) 30% of nominal amplitude. fig.6 response signals for maximum step improvement, no peaking and maximum line width. handbook, halfpage 0 0.5 1000 800 200 0 400 600 1.0 1.5 2.0 t ( m s) v o (mv) (1) (2) mbh233 (1) 90% of nominal amplitude. (2) 30% of nominal amplitude.
1997 dec 01 16 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 fig.7 response signals for no step improvement, maximum peaking and 0% coring. handbook, halfpage 0 0.5 1400 1000 200 - 200 600 1.0 1.5 2.0 t ( m s) v o (mv) (1) (2) mbh234 (1) 90% of nominal amplitude. (2) 30% of nominal amplitude. fig.8 response signals for maximum step improvement, nominal line width, maximum peaking and 0% coring. handbook, halfpage 0 0.5 1400 1000 200 - 200 600 1.0 1.5 2.0 t ( m s) v o (mv) (1) (2) mbh235 (1) 90% of nominal amplitude. (2) 30% of nominal amplitude. fig.9 block diagram of the step improvement processor. handbook, full pagewidth mbh236 minmax selector minmax y envelope y step clamps fader line width control delay yin
1997 dec 01 17 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 fig.10 block diagram of the smart sharpness controller. handbook, full pagewidth mbh237 step detector fader coring y envelope y step y contour y step y c delay cells coring control peaking control smart noise steepness control fig.11 frequency transfers narrow contour filter. handbook, full pagewidth 0 100 mbh238 10 4 10 5 10 6 10 7 f (hz) contour (%) 10 8 20 40 60 80 (1) (2) (1) 1f h mode. (2) 2f h mode.
1997 dec 01 18 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 fig.12 frequency transfers wide contour filter. handbook, full pagewidth 0 100 mbh239 10 4 10 5 10 6 10 7 f (hz) contour (%) 10 8 20 40 60 80 (1) (2) (1) 1f h mode. (2) 2f h mode. fig.13 relative decrease of steepness level as a function of voltage at pin snc starting from four different steepness level presets. handbook, halfpage 0 (%) 25 50 100 v ref (%) 100 50 0 mbh240 75 75 25
1997 dec 01 19 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 fig.14 relative increase of coring level as a function of voltage at pin snc starting from four different coring level presets. handbook, halfpage 0 (%) 25 50 100 v ref (%) 100 80 60 40 20 0 mbh241 75 fig.15 feature setting control as a function of the pin voltage for peaking, coring, steepness and line width. handbook, halfpage 37.5 transfer (%) 50.0 62.5 87.5 v ref (%) 100 50 0 mbh242 75
1997 dec 01 20 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 internal circuitry fig.16 simplified circuit diagram pin 1. handbook, halfpage mbh244 275 w sandcastle 1 fig.17 simplified circuit diagram pin 2. 2 handbook, halfpage mbh245 275 w cor fig.18 simplified circuit diagram pin 3. handbook, halfpage 275 w adext1 mbh246 100 k w 3 fig.19 simplified circuit diagram pin 4. handbook, halfpage mbh247 275 w lwc 4 fig.20 simplified circuit diagram pin 5. handbook, halfpage mbh248 275 w yin 5 fig.21 simplified circuit diagram pin 6. 6 handbook, halfpage mbh249 275 w adr
1997 dec 01 21 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 fig.22 simplified circuit diagram pin 7. handbook, halfpage mbh250 275 w 275 w uin 7 fig.23 simplified circuit diagram pin 8. 8 handbook, halfpage mbh251 275 w 900 w 1 m w cfs fig.24 simplified circuit diagram pin 9. 9 handbook, halfpage mbh252 275 w 275 w vin fig.25 simplified circuit diagram pin 10. handbook, halfpage 275 w adext2 mbh253 100 k w 900 w 10 fig.26 simplified circuit diagram pin 11. n dbook, halfpage mbh254 275 w peak 11 fig.27 simplified circuit diagram pin 12. 12 handbook, halfpage mbh255 275 w scl
1997 dec 01 22 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 fig.28 simplified circuit diagram pin 13. 13 handbook, halfpage mbh256 275 w sda fig.29 simplified circuit diagram pin 14. 14 handbook, halfpage mbh257 275 w 900 w 1 m w ams fig.30 simplified circuit diagram pin 15. 15 handbook, halfpage 275 w snc mbh258 fig.31 simplified circuit diagram pin 16. 16 handbook, halfpage 100 w 0.5 ma vout mbh259 fig.32 simplified circuit diagram pin 17. 17 handbook, halfpage mbh260 275 w 900 w 1 m w fhs fig.33 simplified circuit diagram pin 18. handbook, halfpage 100 w 0.5 ma uout mbh261 18
1997 dec 01 23 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 fig.34 simplified circuit diagram pin 19. handbook, halfpage mbh262 gnd 19 fig.35 simplified circuit diagram pin 20. 20 handbook, halfpage 100 w 0.5 ma yout mbh263 fig.36 simplified circuit diagram pin 21. 21 handbook, halfpage mbh264 v cc fig.37 simplified circuit diagram pin 22. 22 handbook, halfpage mbh265 275 w steep fig.38 simplified circuit diagram pin 23. 23 handbook, halfpage 100 w 21 k w v ref mbh266 fig.39 simplified circuit diagram pin 24. handbook, halfpage 24 100 w 100 w r ext mbh267
1997 dec 01 24 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 application information to benefit optimally from its picture-sharpening capabilities, the TDA9177 should be positioned as the last part of the yuv-chain. feature reduction as a function of the noise contents of the picture can easily be realized in hardware by using a noise detector. smart noise control (snc) can be tailor-made for each application, by means of controlling the peaking and the steepness values by software (i 2 c-bus control). whenever i 2 c-bus control is not feasible, the embedded smart sharpness algorithm can be executed by driving pin snc with the output of a noise detector. in this concept, additional post-processing of the noise detector output can easily be realized with external components. figure 40 shows an application example in which the TDA9177 is bus controlled, with the i 2 c-bus address at 40h. furthermore, the smart noise control pin (snc; pin 15) is not used in the example shown. fig.40 application diagram. handbook, full pagewidth mbh243 24 8 v 0 v 23 22 21 20 19 TDA9177 yout uout vout 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 100 nf yin 100 nf uin 10 nf vin scl sda 10 nf sandcastle 100 m f 10 k w 100 w 100 w
1997 dec 01 25 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot234-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 22.3 21.4 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip24: plastic shrink dual in-line package; 24 leads (400 mil) sot234-1
1997 dec 01 26 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds.
1997 dec 01 27 philips semiconductors product speci?cation yuv transient improvement processor TDA9177 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca56 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 547047/1200/02/pp28 date of release: 1997 dec 01 document order number: 9397 750 03053

▲Up To Search▲

Price & Availability of TDA9177

	To Download TDA9177 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .